Some challenges facing turnaround times for application specific integrated circuit designs are to insure that the designs are timely, syntactically correct, accurate, and have complete timing constraints. Because so many tools are now driven by timing constraints in the back end of design processes, timing constraint deliverables have become as important as netlists to layouts for the circuits.
Conventional solutions involve hand-coding timing constraints based on design knowledge. Hand-coding the constraints involves experience with not only constraint syntax, as each back end tool may read constraints differently, but also familiarity with the design at the given level of back end processing. For instance, some design approaches typically use timing constraints for each level of a design on which timing driven placement and optimization are utilized. Problems can arise for the hand-coding approaches due to a lack of design expertise in the context of the constraints. For example, top level constraints are often the last items to get attention since the top level design is one of the last blocks to be constructed. Another disadvantage is a lack of expertise with a static timing analysis language. Chip vendors commonly teach the customers how to write constraints that are compatible with the tools used by the chip vendor. Constraints are commonly written in many useful ways, yet there is usually a best practice to apply that should be learned for each tool. Furthermore, humans make mistakes and constraints are missed because there is no deterministic, automated methodology to writing the constraints.